AndesCore™ AX45MP

64-bit in-order dual-issue 8-stage pipeline CPU architecture Symmetric multiprocessing up to 8 cores Level-2 cache and cache coherence support AndeStar™ V5 Instruction Set Architecture (ISA) Compliant to RISC-V RV64 GCP little endian RV-GC: Integer, single/double precision floating point and 16-bit extensions RV-P DSP/SIMD extensions (draft) Andes V5 performance/code size extensions Separately licensable Andes Custom Extension™ (ACE) for custom acceleration 64-bit architecture for memory space over 4GB 16/32-bit mixable instruction format for compacting code density Branch predication to speed up control code Return Address Stack (RAS) to speed up procedure returns Memory Management Unit (MMU), Physical Memory Protection (PMP) and programmable Physical Memory Attribute (PMA) Level-1 and level-2 cache controllers with 64-byte cache line size Flexibly configurable Platform-Level Interrupt Controller (PLIC) for supporting wide range of system event scenarios Enhancement of vectored interrupt handling for real-time performance Advanced CoDense™ technology to reduce program code size
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